1. Field of the Invention
The present invention relates to voltage regulators, and more specifically to a compensated voltage regulator for biasing the terminals of electrically-programmable non-volatile memory cells.
2. Description of the Related Art
A conventional electrically-programmable non-volatile memory is constructed as matrices of memory cells that each include a floating gate MOS transistor having drain and source regions. The floating gate is formed over the semiconductor substrate and is isolated from the substrate by a thin layer of gate oxide, and a control gate is capacitively coupled through a dielectric layer to the floating gate. Metal electrodes are provided for contacting the drain, source, and control gate terminals to allow predetermined voltages to be applied to the memory cell. A semiconductor integrated circuit non-volatile memory device typically has a very large number of such cells organized into a matrix of rows (or word lines) and columns (or bit lines). All of the memory cells in one word line have a common drive line connected to their control gates, and the memory cells in one bit line have their drain terminals connected in common.
In conventional non-volatile memory cells, the amount of charge present on the floating gate can be varied by suitably biasing the terminals of the cell. Charge is stored on the floating gate through a "programming" operation in which the drain terminal and the control gate are biased to a predetermined voltage that is higher than the voltage at the source terminal. In particular, the programming or writing of an individual memory cell is based on the well-known phenomenon of hot electron injection in which cell programming is enabled by an injection of hot electrons onto the floating gate.
During programming, hot electrons are generated in the channel of the floating gate transistor in proximity to the drain region when there are present electric fields of such strength that the electrons are given a much different mobility than that caused by normal thermal agitation. For such an electron injection to occur, the electrons must be supplied kinetic energy of a greater magnitude than the potential energy existing between the channel and the gate region. This is achieved by biasing the gate and drain terminals of the memory cell at relatively high voltages (e.g., 12.5V and 6.5V, respectively).
Such memory cell biasing involves considerable dissipation of current and it is vital that the memory cell accessing resistors do not produce voltage drops sufficient to degrade the potential of the bias voltage being applied. If such a degradation does occur in non-volatile memory cells of the flash type for example, the reduced potential of the drain voltage Vpd causes an insufficient or slow programming of the memory cell. On the other hand, too large of a potential for the drain voltage Vpd can cause a destructive snap-back phenomena or the memory cell to be soft erased (i.e., become partially erased). Thus, the optimum range for the drain voltage Vpd is fairly limited with variations on the order of 200 mV to 300 mV from the reference potential being typically dictated by the technology. In this respect, the writing rate and snap-back phenomenon respectively set the lower and upper limits of the drain voltage range that is acceptable for proper programming of the memory cell.
In order to insure that programming voltages fall within the required range, conventional memory devices are provided with a sophisticated type of voltage regulator that is adapted to supply the bit lines of the cell matrix with an accurately regulated drain voltage during programming. However, advanced miniaturizing technologies make it increasingly more difficult to provide programming circuitry that is capable of generating the appropriate bias voltages. In particular, reduced width and thickness interconnect lines result in higher resistance for the conduction paths used for applying the drain voltage to the memory cells. Further, the current dissipation of each memory cell increases as a result of reduced oxide thicknesses.
Such problems become even more acute at the testing stage in which multiple memory cells are simultaneously programmed in parallel in order to lower the cost and time of the operation. More specifically, the simultaneous programming causes increased voltage drops across the conduction paths used for accessing the drain terminals of the memory cells. Furthermore, the reduced channel length brought about by the ongoing miniaturization process significantly restricts the permissible range for the drain voltage mainly because of a lowered snap-back voltage.
A number of programming circuits have been proposed to solve the problems described above. According to one solution that is disclosed in European Patent Application No. 93-830545.5, a drain voltage regulator outputs a slightly higher voltage than the voltage desired for the bit line. This voltage difference is instantaneously dependent on the current actually flowing through the bit line select transistors. A voltage regulator of this type is formed through an adaptive bias technique using a positive feedback structure. The feedback structure employs a "central" generator that includes an average voltage drop compensator for the access lines to the cell drains, and the voltage is regulated using a feedback circuit of the cascode-compensator type.
Additionally, in such a regulator, an outer feedback loop also exists so as to modify the system reference voltage according to the output current. Thus, the generator supplies a higher output voltage with larger output currents to compensate for the voltage drop across the memory cell access lines. However, the bias variation caused by the number and location of memory cells being programmed remains quite high. While being somewhat advantageous, such a regulator applies its voltage control operation to the whole of the memory cells and does not allow the high programming parallelism that is necessary to speed up the testing of the memory device.
In a more recent solution that is disclosed in European Patent Application No. 96-830192.9, local drain voltage generators are employed for each output sector of the memory matrix. An example of programming circuitry incorporating local generators for the drain voltage Vpd is shown in FIG. 1, and a more detailed diagram of the programming circuitry is shown in FIG. 2. In the circuitry of FIG. 2, the Vpp line supplies the high voltage (e.g., 12.5V) for the programming operation and is used to generate a reference voltage Vref (e.g., 6.5V by dividing the program voltage Vpp). The reference voltage Vref potential is "duplicated" with low output resistance by multiple drain voltage Vpd generators.
The drain voltage generators are located adjacent to the memory matrix so that the access path to the memory cell drains is much shorter than in device arrangements having a "central" generator and providing long signal distribution paths and transistors for accessing the matrix sectors containing memory cells to be programmed. Furthermore, with this arrangement, the memory cell biasing is not affected by the number and location of the output sectors that are involved in the programming. This advantage also holds true for parallel programming because it is possible to activate several independent paths at the output of each generator by acting on column selection.
The structure used in FIG. 2 includes a negative feedback regulator that can smooth out the output voltage Vyms to close to the reference voltage Vref for even large output currents. The high differential gain of the comparator, the ample dynamic range of its output signal, and the high transconductance of the cascodes ensure regulation even in situations of considerable drift of the technological parameters and degradation of the supply voltage Vpp. Further, a capacitor at the comparator output creates a dominant time constant in the feedback network that prevents overshooting at both the transient and the regulation phases, and enable transistors controlled by a program signal inhibit the generator action when the data to be written into the memory cell is the same as the state of a virgin memory cell.
Although this solution provides such advantages, it may also be unsatisfactory where the resistance downstream of the generators becomes too high. For example, a voltage drop can occur across the whole of Vpp line in a device having very long bit lines or when the current drain of the memory cells is quite large (e.g., in parallel programming). Such an overall voltage drop causes the reference voltages to be degraded and thus results in an unacceptable variation in the programming voltage.